Dynamically Reconfigurable Processor Technology for Vision Processing

Wednesday, May 22, 1:35 PM - 2:05 PM
Summit Track: 
Enabling Technologies
Exhibit Hall ET 1

The Dynamically Reconfigurable Processing (DRP) block in the Arm Cortex®-A9 based RZ/A2M MPU accelerates image processing algorithms with spatially-pipelined, time-multiplexed reconfigurable-hardware compute resources. This hybrid ARM/DRP architecture combines the economy, flexibility and ease-of-use of microprocessors with the high throughput and low latency of performance-optimized hardware. DRP technology achieves silicon area efficiency by dividing large data paths into sub-blocks that can be swapped into the DRP hardware on each clock cycle to accelerate multiple complex algorithms while avoiding the cost and power penalties associated with large FPGAs. Pre-built libraries and a C-language programming environment deliver these benefits without the need for hardware design expertise. Designs can be iteratively enhanced through pre-production and even after mass-market deployment. We examine the DRP block’s architecture and operation, present benchmarks demonstrating performance up to 20x greater than traditional CPUs and introduce resources for developing DRP-based embedded vision systems with the RZ/A2M MPU.


Yoshio Sato

Sr. Product Marketing Manager, Industrial Business Unit, Renesas

Yoshio Sato is a Senior Product Marketing Manager in the Industrial Business Unit of Renesas. Sato is a fact-based, analytical and strategic senior marketing professional with wide global experience and deep technical knowledge. He has 13 years of experience in microprocessor product marketing and business development, and 10 years of experience in technical roles in supercomputer chip testing, automotive SOC design and technical support for tier-1 automotive customers.

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