Memory-centric Hardware Acceleration for Machine Intelligence

Wednesday, May 22, 1:00 PM - 1:30 PM
Summit Track: 
Enabling Technologies
Location: 
Exhibit Hall ET 1

Even the most advanced AI chip architectures suffer from performance and energy efficiency limitations caused by the memory bottleneck between computing cores and data. Most state-of-the-art CPUs, GPUs, TPUs and other neural network hardware accelerators are limited by the latency, bandwidth and energy consumed to access data through multiple layers of power-hungry and expensive on-chip caches and external DRAMs. Near-memory computing, based on emerging nonvolatile memory technologies, enables a new range of performance and energy efficiency for machine intelligence. In this presentation, we introduce innovative and affordable near-memory processing architectures for computer vision and voice recognition, and also present architectural recommendations for edge computing and cloud servers. We also discuss how non-volatile memory technologies, such as Crossbar Inc.’s ReRAM, can be directly integrated on-chip with dedicated processing cores, enabling new memory-centric computing architectures. The superior characteristics of ReRAM over legacy non-volatile memory technologies help to address the performance and energy efficiency demands of machine intelligence at the edge and in the data center. 

Speaker(s):

Sylvain Dubois

Vice President, Business Development and Marketing, Crossbar

Sylvain Dubois joined Crossbar in 2013 as Vice President of Strategic Marketing and Business Development. With 18 years of experience in semiconductor business development and strategic product marketing, he brings a proven ability to analyze market trends, identify new, profitable business opportunities and create product positioning that is in sync with markets demands to drive market share leadership and business results. Prior to Crossbar, Dubois led strategic product positioning and market engagement for new products at Spansion. Responsible for identifying growth opportunities and expanding the product portfolio, he was instrumental in defining the Spansion flash memory roadmap. From 2002-2006, Dubois was a system-on-chip architect at Texas Instruments, in charge of the architecture and technology roadmap of DRAM and flash memory controllers within the OMAP application processors, and also responsible for developing strategic relationships with DRAM and flash memory suppliers. Dubois holds an MS degree in microelectronics from E.S.I.E.E. (Paris), University of Southampton (UK) and Universidad Pontifica Comillas (Spain).

See you at the Summit! May 18-21 in Santa Clara, California!